1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device including a programmable element, and a technique for achieving both a reduction of leak current and a decrease of the area of the programmable element. In particular, the present invention relates to a technique for achieving both a decrease of the area of a fuse element or the like and a reduction of leak current flowing through a residual resistance thereof in a memory block on which a plurality of programmable elements have to be mounted for redundancy repair.
2. Description of the Related Art
Conventionally, in general, a fuse element is utilized as a programmable element, for example, used in a memory block, and the presence or the absence of a program generally is set by either irradiating the fuse element with laser to melt and cut (blow) the fuse element or not doing so. However, in order to blow the fuse element with high precision, it is necessary to adjust the power of the laser for irradiation.
FIGS. 12A, 12B and 12C are circuit diagrams showing an example of the configuration of a conventional programmed value determining circuit employing a fuse element as a programmable element used in a memory block and the like. FIG. 12A shows a state in which there is no program before a fuse element 100 is blown. FIG. 12B shows a state in which there is a program after the fuse element 100 has been blown with a high laser power. FIG. 12C shows a state in which there is a program after the fuse element 100 has been blown with a low laser power.
In FIG. 12A, when a voltage with a logic xe2x80x9cHxe2x80x9d level is applied to an input node N1, a PMOS transistor Qp1 in the first stage is turned off, and an NMOS transistor Qn1 in the first stage is turned on. Since the fuse element 100 is connected, an intermediate node (storage node) N2 is in a logic xe2x80x9cLxe2x80x9d level, which is the electric potential of the ground line VSS, and a PMOS transistor Qp3 in the second stage is turned on and an NMOS transistor Qn2 in the second stage is turned off, so that a voltage with a logic xe2x80x9cHxe2x80x9d level, which is the electric potential of the power line VDD, is output to an output node N3. Thus, a PMOS transistor Qp2 is turned off. This is the state in which there is no program.
On the other hand, in FIGS. 12B and 12C in which the fuse element 100 is blown, when a voltage with a logic xe2x80x9cHxe2x80x9d level is applied to an input node N1, a PMOS transistor Qp1 in the first stage is turned off, and an NMOS transistor Qn1 is turned on. However, since the fuse element 100 is cut off, the intermediate node N2 becomes in a logic xe2x80x9cHxe2x80x9d level, which is the electric potential of the power line VDD, by turning the PMOS transistor Qp2 on, and the PMOS transistor Qp3 in the second stage is turned off and an NMOS transistor Qn2 in the second stage is turned on, so that a voltage with a logic xe2x80x9cLxe2x80x9d level, which is the electric potential of the ground line VSS is output to an output node N3. This is the state in which there is a program.
As shown in FIG. 12B, in order to blow the fuse element 100 completely (the residual resistance of the fuse element 100 is, for example, 1 M ohm or more), it is sufficient to increase the power of the laser for irradiation, but the fuse elements in the vicinity thereof may be melted and cut. Therefore, when providing a plurality of fuse elements, the area may increase because the distance between the adjacent fuse elements is increased or transistors cannot be laid out in the adjacent regions.
On the other hand, when the power of the laser for irradiation is low, an irradiation point also is small, so that the influence on the adjacent region can be small. However, the residual resistance of the fuse element 100 becomes low (e.g., 10 k ohm or less), so that a leak current Ileakflows from the power line VDD to the ground line VSS through the PMOS transistor Qp2 and the NMOS transistor Qn1, as shown in FIG. 12C.
FIG. 13 is a graph showing the relationship of the residual resistance Rfuse and the leak current Ileak caused to flow thereby after the fuse element 100 has been blown, with respect to the fuse pitch Hpitch and the relative laser power Lpower.
As shown in FIG. 13, when the fuse pitch Hpitch is small and the relative laser power Lpower is small, the fuse element 100 is melted and cut completely in some cases, and in other cases, it is not completely melted and cut, which creates instability, so that the residual resistance Rfuse are varied significantly. In particular, when the residual resistance Rfuse becomes small, the leak current Ileak becomes large. Therefore, conventionally, there is a trade-off between the fuse pitch Hpitch, that is, the area and the leak current Ileak.
In the future, process miniaturization will be promoted, and a large number of functions will be integrated. With this trend, it becomes more important to constitute a circuit that implements a defect recovery function with FPGA (Field Programmable Gate Array) or the like, so that it is expected that a demand for program elements that are mounted on an LSI will be increased rapidly. In this case, the area of the programmable elements will be an issue.
In addition to blowing the fuse element as described above, in order to form a programmable element, a polysilicon line can be melted and cut by applying a high voltage, or a high voltage stress is applied to increase the threshold voltage, as is the case with a flash memory. However, in all of these methods, the programmable element has to be spaced apart from adjacent devices or the area thereof has to be increased in order to change the resistance or the threshold voltage stably.
When reducing the area to increase the degree of integration, the change in the resistance of the polysilicon line or the change in the threshold voltage of the flash memory may become insufficient, and the problem of leak current is likely to be induced.
Therefore, with the foregoing in mind, it is an object of the present invention to provide a programmed value determining circuit in which there is no relationship of a trade-off between the area of the programmable element and the leak current, and both the area of the programmable element and the leak current are reduced, and provide a semiconductor integrated circuit device having the programmed value determining circuit and a method for determining a programmed value.
A programmed value determining circuit of the present invention includes a programmable element whose resistance is changed depending on whether or not there is a program, a detecting portion including a first circuit and a second circuit, and latch means. The first circuit includes first and second switching elements that operate in response to first and second control signals respectively, and are connected to the program element in series between a first power terminal and a second power terminal. At least the first switching element is inserted between the first power terminal and an intermediate connection node. At least the second switching element connected to the programmable element in series is inserted between the intermediate connection node and the second power terminal. The second circuit converts an electric potential at the intermediate connection node to a logic level and outputting it to an output node. The latch means latches the electric potential at the intermediate connection node to make the intermediate connection node act as a storage node of a programmed value of the programmable element. During a second period subsequent to the first period after power is turned on, at least the second switching element is turned on, the storage node is connected to the second power terminal via the programmable element, and the state of the storage node is detected by the detecting portion. During a third period after the second period, both the first and the second switching elements are turned off, and the state of the storage node is held by the latch means.
In the programmed value determining circuit of the present invention, during the first and the third periods, the opposite terminals of the programmable element are disconnected from at least one of the first and the second power terminals. During the second period, each of the opposite terminals of the programmable element is connected to the first or the second power terminal directly or via the first or the second switching element.
In the programmed value determining circuit of the present invention, the first switching element is constituted by a first transistor controlled in response to the first control signal. The second switching element is constituted by a second transistor controlled in response to the second control signal. The storage node is connected to the first power terminal via the first transistor and is connected to one terminal of the programmable element via the second transistor, and the other terminal of the programmable element is connected to the second power terminal. The first transistor is turned off during the first period, turned on during the second period, and turned off during the third period in response to the first control signal. The second transistor is turned off during the first period, turned on during the second period, and turned off during the third period in response to the second control signal.
This configuration makes the following control possible. The second period during which the state of the program of the programmable element is detected is restricted to a predetermined period during power-on, and only during this period, the storage node of the programmed value is connected to one power terminal via the programmable element. However, during the other periods, such as the first and the third periods, the storage node is disconnected therefrom, and the programmable element is disconnected completely from leak paths between the power terminals. Thus, the relationship of a trade-off between the area of the programmable element and the leak current can be eliminated, and both the area of the programmable element and the leak current can be reduced.
In the programmed value determining circuit of the present invention, the first switching element is constituted by a first transistor controlled in response to the first control signal, and the second switching element is constituted by a second transistor controlled in response to the second control signal. The storage node is connected to the first power terminal via the first transistor and is connected to one terminal of the programmable element via the second transistor, and the other terminal of the programmable element is connected to the second power terminal. The first transistor is turned on during the first and the second periods and turned off during the third period in response to the first control signal. The second transistor is turned off during the first period, turned on during the second period, and turned off during the third period in response to the second control signal.
According to this configuration, the storage node can be precharged to the logic xe2x80x9cHxe2x80x9d level, for example, from the power line VDD via the first transistor, before the second period starts, regardless of the presence or the absence of a program. Therefore, the determination as to whether or not there is a program during the second period can be performed stably.
In the program value determining circuit of the present invention, the latch means includes a third circuit connected between the intermediate connection node and the output node. The third circuit and the second circuit cooperate to make the intermediate connection node act as the storage node of the programmed value.
In this case, the third circuit is connected to the first and the second power terminals via signal lines that transmit third and fourth control signals for power supply. Furthermore, it is preferable that the first and the second control signals are delayed with respect to the third and the fourth control signals, the first and the second control signals have a logically inverse relationship, and the third and the fourth control signals have a logically inverse relationship.
According to this configuration, the current load of the latch means is disconnected from the storage node of the detecting portion at a time td before the second period starts, and the latch means latches the state of the storage node before it disappears at a time td before the second period ends. Thus, a stable operation of determining a programmed value can be achieved. These four control signals have a delay and a logically inverse relationship, so that they can be generated easily.
In the programmed value determining circuit of the present invention, a current flowing through the programmed value determining circuit during the third period is defined by the leak current of the latch means or the off-current of the first and the second switching elements.
According to another aspect of the present invention, a first semiconductor integrated circuit device of the present invention, for which an acceptable value of a leak current flowing per program element is set, includes the programmed value determining circuit of the present invention. The programmed value determining circuit determines that there is no program when a current flowing at a time of applying a voltage in a vicinity of a power voltage to the programmable element exceeds the acceptable value of the leak current, and determines that there is a program when the current is not more than the acceptable value of the leak current, and the programmed value determining circuit outputs either one of binary logic levels to a functional circuit as a result of the determination.
In this case, the first semiconductor integrated circuit device is a semiconductor memory device having a plurality of regular memory blocks and a redundant memory block. The functional circuit is a redundancy repair circuit for replacing a regular memory block with a defect by an adjacent regular memory block or the redundant memory block.
According to this configuration, when a fuse element is used as the programmable element in which it is determined that there is a program when the fuse element is cut by being blown with laser irradiation, a shift redundancy repair circuit to which the program value determining circuit without the problem of leak current is applied can be achieved, and power consumption during a stand-by time of the semiconductor memory can be reduced.
A second semiconductor integrated circuit device of the present invention, for which an acceptable value of a current flowing per programmable element is set, includes the programmed value determining circuit of the present invention. The programmed value determining circuit determines that there is no program when a current flowing at a time of applying a voltage in a vicinity of a power voltage to the programmable element is not more than the acceptable value of the current, and determines that there is a program when the current exceeds the acceptable value of the current, and the programmed value determining circuit outputs either one of binary logic levels to a functional circuit as a result of the determination.
In this case, the second semiconductor integrated circuit device is a semiconductor memory device having a plurality of regular memory blocks and a redundant memory block. The functional circuit is a redundancy repair circuit for replacing a regular memory block with a defect by an adjacent regular memory block or the redundant memory block.
According to this configuration, when an element in which it is determined that there is a program when the element is short-circuited by gate breakdown is used as the programmable element, this case has the opposite relationship in the leak current to the case where a fuse element is used as the programmable element.
A third semiconductor integrated circuit device of the present invention in which one chip is divided into a plurality of circuit blocks having different power systems includes a first circuit block and a second circuit block. In the first circuit block, a first programmed value determining circuit of the present invention is provided and power is turned repeatedly on and off. In the second circuit block, a second programmed value determining circuit having the same configuration as that of the first programmed value determining circuit is provided, and the number of times that power is turned off is lower than that in the first circuit block. The first programmed value determining circuit has at least one each of the first, the second and the third periods for only a predetermined period between power-on and power-off.
This configuration makes it possible to reduce power consumption significantly by applying the programmed value determining circuit without the problem of leak current to an LSI in which a power saving function is emphasized and power is turned repeatedly on and off with respect to a part of the mounted circuits.
A fourth semiconductor integrated circuit device in which one chip is divided into a plurality of circuit blocks having different power systems includes a first circuit block and a second circuit block. In the first circuit block, power is turned repeatedly on and off, and in the second circuit block, the number of times that power is turned off is lower than that in the first circuit block. The second circuit block includes a first programmed value determining circuit of the present invention corresponding to the first circuit block and a second programmed value determining circuit having the same configuration as that of the first programmed value determining circuit and corresponding to the second circuit block.
According to this configuration, the first and the second programmed value determining circuits are provided in the second circuit block in which the number of times that power is turned off is lower than that in the first circuit block, so that there is no possibility that the storage capability of the program may deteriorate, compared with the third semiconductor integrated circuit device in which a current flows through the programmable element every time power is turned on, and the reliability of the program can be improved and power saving can be promoted further.
A fifth semiconductor integrated circuit device of the present invention is of a multi-chip type and includes a plurality of chips including at least first and second chips. The second chip is attached to the surface of the first chip with its surface facing downward and is connected electrically. The first chip includes a first circuit block, and the second chip includes a second circuit block. The first circuit block includes a first programmed value determining circuit of the present invention corresponding to the first circuit block and a second programmed value determining circuit having the same configuration as that of the first programmed value determining circuit and corresponding to the second circuit block.
According to this configuration, in the semiconductor integrated circuit device having a chip-on-chip (COC) structure, in addition to the advantages of the programmed value determining circuit of the present invention, there is another advantage that a program can be provided easily by laser irradiation or the like with respect to the programmable element of the second programmed value determining circuit, for example, for the purpose of performing redundancy repair with respect to a memory block included in the second circuit block, even after the second chip is attached to the surface of the first chip with its surface facing downward.
In the third to the fifth semiconductor integrated circuit devices, the timings of the first and the second control signals are different among a plurality of programmed value determining circuits including the first and the second programmed value determining circuits.
This configuration makes it possible to prevent the logic level determination of the storage node from malfunctioning due to current flowing simultaneously through the plurality of programmable elements and the subsequent voltage drop during the second period.
A sixth semiconductor integrated circuit device of the present invention is of a multi-chip type in which a chip module including a plurality of chips arranged in a plane is mounted on a substrate. The plurality of chips have a plurality of corresponding circuit blocks, and a circuit block located nearest to a power circuit configured on the substrate of the plurality of circuit blocks includes a first programmed value determining circuit of the present invention corresponding to this circuit block and a second programmed value determining circuit having the same configuration as that of the first programmed value determining circuit and corresponding to another circuit block.
This configuration can provide the following advantages, in addition to the advantages of the programmed value determining circuit of the present invention. In the semiconductor integrated circuit device in which a multichip module (MCM) is mounted on a substrate, a plurality of programmed value determining circuits are integrated onto one chip so that the programmable elements of the programmed value determining circuits can be provided with a program easily. Furthermore, if the chip in which a plurality of programmed value determining circuits are integrated is located nearest to the power circuit that generates a high voltage or a large current, a high voltage or a large current can be supplied easily without requiring an extra area or an additional process for increasing the withstand voltage when determining a programmed value, compared with the case in which the programmed value determining circuits are distributed.
It is preferable that in the sixth semiconductor integrated circuit device, the timings of the first and the second control signals are different among a plurality of programmed value determining circuits including the first and second programmed value determining circuits.
This configuration makes it possible to prevent the logic level determination of the storage node from malfunctioning due to current flowing simultaneously through the plurality of programmable elements and the subsequent voltage drop during the second period.
According to another aspect of the present invention, a method for determining a programmed value uses a programmable element whose resistance is changed depending on whether or not there is a program, a first circuit, a second circuit, and latch means. The first circuit includes first and second switching elements that operate in response to first and second control signals respectively, and are connected to the programmable element in series between a first power terminal and a second power terminal. At least the first switching element is inserted between the first power terminal and an intermediate connection node. At least the second switching element connected to the programmable element in series is inserted between the intermediate connection node and the second power terminal. The second circuit converts an electric potential at the intermediate connection node to a logic level and outputs it to an output node. The latch means latches the electric potential at the intermediate connection node and makes the intermediate connection node act as a storage node of a programmed value of the programmable element. The method includes the steps of turning at least the second switching element on, connecting the storage node to the second power terminal via the programmable element, and detecting the state of the storage node by the first and the second circuits during the second period subsequent to the first period after power is turned on; and turning both the first and the second switching elements off, and holding the state of the storage node by the latch means during a third period after the second period.
According to this method, the second period during which the state of the program of the programmable element is detected is restricted to a predetermined period during power-on, and only during this period, the storage node of the programmed value is connected to one power terminal via the programmable element. However, during the other periods including the first and the third periods, the storage node is disconnected therefrom, and the programmable element is disconnected completely from leak paths between the power terminals. Thus, the relationship of a trade-off between the area of the programmable element and the leak current can be eliminated, so that both the area of the programmable element and the leak current can be reduced.